Reddit mentions of Logic Design and Verification Using SystemVerilog

When you start programming the FPGA, I would definitely start with SystemVerilog, there are some really good resources on it, and it is even easier to pick up than Verilog, but gets the same thing done. By and large the tools from Xilinx and Altera get the same thing done as well, but I wouldn't completely write off the Xilinx toolchain. You should also expect to spend most of your learning time at first inside of the simulator, and even when you think you know what you are doing the simulator is an invaluable tool. For learning the ins and outs of SystemVerilog, the FPGA itself is really just a way to demonstrate what you've built, 95% of the learning can happen without it. You will probably also hear a lot about synthesizable vs. non-synthesizable SystemVerilog, for that I would definitely recommend https://www.amazon.com/Logic-Design-Verification-Using-SystemVerilog/dp/1500385786 as its what Carnegie Mellon uses to start off their digital logic classes.

Edit: Also the Pynq board is a great place to start learning about SoC development, while still having high level resources like Python and Linux available should you need them for a project.
http://store.digilentinc.com/pynq-z1-python-productivity-for-zynq/